1. Field of the Invention
The present invention relates to a level shift circuit, and more particularly, to a level shift circuit with voltage pulling.
2. Description of the Related Art
FIG. 1 shows a conventional level shift circuit 1, used in a scan driver of an LCD (Liquid Crystal Display) module, to convert a low-voltage digital signal into a high-voltage digital signal. The level shift circuit 1 includes four HV (high voltage) MOS transistors T1-T4 coupled to each other. The sources of two HV PMOS transistors T1 and T2 receive a first voltage VDDA (e.g., 9 volts or 14 volts). The sources and bulks of two HV NMOS transistors T3 and T4 are connected to a ground level VSSA. When an input signal IN with a low-voltage high state (e.g., 3.3 volts) is applied at the gate of the HV NMOS transistor T3, the HV PMOS transistor T2 is turned on by the gate thereof being grounded through the conductive HV NMOS transistor T3. The HV NMOS transistor T4 is turned off by an inverse signal INB (an inverse signal of the input signal IN) with a low-voltage low state (i.e., 0 volts) applied at the gate thereof. Therefore, an output signal DDX exhibits a high-voltage high state of the first voltage VDDA. In the meantime, the HV PMOS transistor T1 is turned off with the gate thereof at the first voltage VDDA. That is, a low-voltage high state (e.g., 3.3 volts) is converted into a high-voltage high state (e.g., 9 volts or 14 volts) by the level shift circuit 1. When the input signal IN switches to the low-voltage low state (i.e., 0 volts) and the inverse signal INB switches to the low-voltage high state (e.g., 3.3 volts), the HV NMOS transistor T3 is turned off and the HV NMOS transistor T4 is turned on. The HV PMOS transistor T1 is turned on by the gate thereof being grounded through the conductive HV NMOS transistor T4, and the HV PMOS transistor T2 is turned off by the gate thereof receiving the first voltage VDDA through the conductive HV NMOP transistor T1. Therefore, the output signal DDX exhibits a high-voltage low state (i.e., 0 volts). That is, a low-voltage low state (i.e., 0 volts) is converted into a high-voltage low state (i.e., 0 volts) by the level shift circuit 1.
When the inverse signal INB switches from the low-voltage low state to the low-voltage high state (i.e., switches from 0 volts to around 1.6 volts) in some low-voltage applications, the HV NMOS transistor T4 that has a threshold voltage of around 1.4 volts is not easily turned on. This results in some issues. First, the time in which the output signal DDX switches from the high state to the low state is increased. Second, it is possible to generate a DC current path at a moment when all four HV transistors T1-T4 are turned on. Third, a large current dissipates due to the first two issues. Fourth, switching states fails due to the DC current latch. One conventional solution proposed is to add a charge pump to boost the voltage level of the input signal IN and the inverse signal INB from 1.6 volts to 3.2 volts, for example. However, the nature of the low-voltage application causes the accumulated charge by the charge pump to be limited. Consequently, a large capacitor (equivalent to a large area) is needed for this solution.